ST
INV_ST
TT

This option selection determines which clock signal, and/or which phase of that clock signal, will be used to control the sampling of the transmit data presented by the DTE. The best choice for this option is most often determined by factors outside the IDCSU, therefore it may be necessary to try varying this option while monitoring the far end DTE device for reports of received errors.

In all cases the IDCSU will present a clock signal to the DTE, the source of that transmit clock signal is determined by the timing option, not by this option. No matter what selection is made here: ST, INV-ST or TT, it will not change the phase or the frequency of the Transmit Clock signal being sent to the DTE.

If ST is selected the IDCSU will sample the transmit data lead, in order to determine if the DTE is sending a one or a zero, at the instant of the negative going transition of the transmit clock signal. This is the selection which is most often used. The lower the data rate of the port and the shorter the cable from the DTE to the port; the greater the chance that ST will be the optimum setting.

If INV-ST is selected the IDCSU will sample the transmit data lead during the positive going transition of the transmit clock signal. This is one half of a clock cycle later than the negative going transition which is used for ST. The INV-ST option is used in order to compensate for delay in the DTE itself and/or especially delay caused by the length of the DTE to IDCSU cable. With higher data rates, longer cables or the combination of high data rate and a long cable, the probability that INV-ST will be the best option to choose increases.

Factors such as cable capacitance per foot, inductive reactance in the cable, conductor thickness (gauge) and especially cable length will all factor in to the phase relationship between the transmit clock signal being sent by the IDCSU and the transmit data arriving at the transmit data leads. There are too many variables and too many unknown factors to be able to make hard and fast rules for selecting the choice between ST and INV-ST.

If the ideal selection has been made then the IDCSU will always be sampling the transmit data lead at a point near the middle of each transmit data bit. This insures that the IDCSU will correctly sense whether the DTE has presented a ONE or a ZERO during that bit time and no sampling errors will occur.

If the value selected is other than ideal the IDCSU may be sampling the transmit data lead at or near the transition between one bit and the next. This will cause errors because the IDCSU may sense what is actually a ONE as a ZERO or vice versa. Longer cables and higher data rates cause more rounding of the otherwise square transitions from one bit to the next. Poorer quality DTE cables have higher capacitance per foot which accelerates the rounding off effect on pulse edges. This means that even as the width of a data bit is decreasing, the portion of that data bit that may be used to reliably sample is also decreasing. Thus the higher the data rate the more critical this selection becomes.

Manufacturers of well designed DTE equipment are aware that these sampling issues exist. If a DTE manufacturer chooses to implement it, a solution may be made at a very minimal cost. This brings us to a discussion of the TT option.

In the case of receive data and the relationship to receive clock, long cables do not present problems of this sort. This is because both the receive data and the receive clock originate in the DCE, travel the same length of cable and are subjected to the same delay. They arrive at the DTE still perfectly in phase with each other. Transmit data presents a different case, the transmit clock signal is generated by the DCE. It must travel the (unknown) length of cable to reach the DTE being subject to (unknown) delay. The DTE does not react to transitions of transmit clock until they reach it, some delay will always be present. Once the DTE senses a clock transition it presents the next data bit which is to be transmitted. This data must now travel the length of cable in the opposite direction so that it hopefully will arrive at the DCE before it samples again.

Some manufacturers, among them Cisco Systems, take the transmit clock signal which is provided by the DCE and loop it back toward the DCE on an optional third pair of clock leads. In V.35 this pair is SCTE (Serial Clock Transmit External) plus and minus; in RS449 they are called TT (Terminal Timing). This is the actual clock signal which the DCE originally sent, so it is at the same frequency, but it is subjected to the same exact delay and waveshape distortion as the transmit data, since it travels the same length of cable.

When TT is selected the IDCSU looks to SCTE or TT for a clock signal and uses that clock to control when it samples transmit data. Since this clock is expected to be perfectly in phase with transmit data it solves the sampling issues described above. Therefore Verilink Tech Support recommends selecting this option whenever the DTE presents this optional third clock signal.